So-called "rotating head" recorders to which the circuit of the invention applies comprise a cylindrical drum around which the tape is wound helically at a given helix angle, a rotary disk coaxial with the drum and disposed in an equatorial slot, and magnetic heads fixed to the periphery of the disk to project slightly from the surface of the drum so as to bear against the tape. Given the linear displacement of the tape and the rotation of the heads, data is recorded on the tape in sloping track segments, referred to as "frames" by the person skilled in the art. The frames are made up in a given format (slope, number of bits) and also include identification and synchronization data.
The electrical circuit of the invention has its input connected to said transmitter means and has its output connected to a magnetic recording head in contact with the magnetic tape, and is intended firstly to format the data to enable it to be recorded on the tape in a given format, and secondly to encode the data in order to provide error correction.
To this end, the data is stored temporarily in conventional manner in working memory (in the form of a matrix). Encoding is performed by using mathematical operations (known per se, e.g. of the Reed-Solomon code type) for calculating respective redundancy bytes for each line and for each column. Thus, for example, for a matrix of 118 lines by 153 columns, the 118 bytes of each column have ten vertical redundancy bytes associated therewith, and the 153 bytes of each line have 8 horizontal redundancy bytes associated therewith.
The bytes from the data transmitter means are stored column by column one after another in the matrix memory, and they are then removed therefrom line-by-line in order to be recorded on the tape in a given frame configuration.
Encoding performed in this way makes it possible to detect or correct (by decoding) data that is erroneous or lost due to a failure by the recorder and/or to local defects on the tape. By writing the data into the memory in columns and then reading it out in lines, the effects of several consecutive wrong bytes are minimized. It will be understood that the greater the number of redundancy bytes, the better the error correction, but also the longer the time required for encoding the data.
A prior art circuit of this type is shown in block form in FIG. 2 and comprises, in succession: a first encoding circuit 1 for performing vertical encoding (calculating vertical redundancy bytes); working memory 2 in which the bytes are stored in the form of a matrix; a second encoding circuit 3 for performing horizontal encoding (calculating horizontal redundancy bytes); and a data formatting and synchronization circuit "S" whose output is connected to a magnetic head "T".
The memory 2 receives the data bytes together with the vertical redundancy bytes as calculated by the first encoding circuit 1 on a column-by-column basis; these bytes are then extracted (or read) from the memory 2 line-by-line and injected into the second encoding circuit 3 which calculates the horizontal redundancy bytes. At its output, the second encoding circuit 3 delivers both the horizontal redundancy bytes and the contents of the memory 2. The entire set of data bytes, vertical redundancy bytes, and horizontal redundancy bytes is then processed by the circuit S prior to being recorded on the tape by the magnetic head T.
This prior circuit suffers from drawbacks.
Assume that the data stream arriving at the vertical encoder circuit 1 has a frequency "f", then the output stream from the circuit 1 has a frequency f.sub.1 =f. (118+10)/118 (for a 118 line matrix having 10 vertical redundancy bytes); f.sub.1 is greater than f. Consequently, a data compression circuit 4 is provided upstream from the first encoding circuit 1 in order to contrive periodic "blank" time intervals for containing the calculated vertical redundancy bytes. Similarly, the horizontal encoder circuit 3 receives a data stream of frequency f.sub.1 at its input while its output delivers a stream at frequency f.sub.2 =f.(118+10)/118.times.(153+8)/153, giving f.sub.2 greater than f.sub.1. The memory 2 also serves to make the frequency change from f.sub.1 to f.sub.2 possible and this function may be thought of as being provided by a virtual second data compression circuit 5 integrated within the memory 2. Such "data compression" circuits are better known from the abbreviation FIFO (for first-in first-out buffer memory).
The need to provide such data compression circuits complicates the formatting circuit overall.
In addition, it follows from the above, that the vertical encoder circuit processes data at a frequency which is different from that of the horizontal encoder circuit. This further increases the complexity of implementing these two circuits.
Furthermore, the trend in the recording technology with which this type of circuit is used is towards ever higher data rates, e.g. several hundred megabit/s and even one gigabit/s.
Given the frequency difference (associated with the data rate) between the input and the output of the first encoding circuit, the first encoding circuit imposes an upper limit on operating frequency which is lower than that required (as mentioned above). In order to reach the required frequencies, it might be assumed that multiple input channels could be provided so as to enable the encoding circuit to process data in parallel. However, this would be possible only at the cost of increasing the complexity of the first encoder circuit. In any event, electronic technology imposes a limit as to the number of bytes which can be processed in parallel.
The invention seeks to remedy this drawback and proposes a circuit for encoding and formatting data, which circuit is simple in structure and operation, and is suitable for operating at high data rate values.